1. Field of the Invention
The present invention relates to a method of inspecting the stitching (or connecting) accuracy in stitched pattern elements that are lithographically formed in desired regions successively on a semiconductor wafer, a liquid crystal panel, a mask, or the like, using an exposure system, such as an electron-beam lithography system during the process of fabrication of semiconductor devices, a mask, or the like.
2. Description of the Related Art
In an electron-beam lithography machine, an electron beam is deflected according to a desired pattern. Thus, the desired pattern is drawn. A variable-shaped beam (VSB) lithography machine is one such electron-beam lithography machine. In the VSB lithography machine, a deflector mounted between two rectangular apertures shapes the cross section of an electron beam into a rectangle.
In particular, the image of the first rectangular aperture is projected onto the second rectangular aperture. The electron beam passed through the first rectangular pattern is deflected to vary the projection position on the second rectangular aperture. An electron beam having a different cross-sectional area is formed. This shaped electron beam is directed (shot) onto a material on which a desired pattern is to be drawn.
One example of a variable-shaped beam lithography machine is shown in FIG. 1, where an electron gun 1 emits an electron beam EB that is directed onto a first shaping aperture 3 via an illumination lens 2.
The image of the aperture of the first shaping aperture is focused onto a second shaping aperture 5 by a shaping lens 4. The position of the focus can be varied by a shaping deflector 6. The image shaped by the second shaping aperture 5 is directed onto a material 9 on which a desired pattern is to be drawn, via a reduction lens 7 and via an objective lens 8. The position on the material 9 struck by the image can be changed by a positioning deflector 10.
A control CPU 11 routes pattern data from a pattern data memory 12 to a data transfer circuit 13. The pattern data from the data transfer circuit 13 is sent to a control circuit 14, another control circuit 15, a further control circuit 16, and a blanking control circuit 18. The control circuit 14 controls the shaping deflector 6. The control circuit 15 controls the positioning deflector 10. The control circuit 16 controls excitation of the objective lens 8. The blanking control circuit 18 controls a blanking electrode 17 for blanking the electron beam generated from the electron gun 1.
A shot (exposure) time correcting memory 19 is connected with the blanking control circuit 18. The blanking signal from the blanking control circuit 18 is corrected according to the value from the shot time correcting memory 19. The control CPU 11 controls a driver circuit 21 for a stage 20 on which the material 9 is placed, to move the material across each field. The operation of this structure is next described.
The fundamental drawing operation is first described. Pattern data stored in the pattern data memory 12 is read out successively and sent to the data transfer circuit 13. The deflection control circuit 14 controls the shaping deflector 6 according to the data from the data transfer circuit 13. The control circuit 15 controls the positioning deflector 10.
As a result, the cross section of the electron beam is shaped into each individual element of the desired pattern by the shaping deflector 6. The elements of the pattern are successively shot onto the material 9, thus drawing the desired pattern. At this time, a blanking signal is sent from the blanking control circuit 18 to the blanking electrode 17, so that the electron beam is blanked in synchronism with the bombardment of the material 9 by the electron beam.
Where a different region on the material 9 is written lithographically, an instruction is given from the control CPU 11 to the stage driver circuit 21, causing the stage 20 to move a desired distance. The distance traveled by the stage 20 is monitored by a laser interferometer (not shown). The position of the stage is accurately controlled according to the results of measurements obtained by the laser interferometer.
Where a pattern is drawn on a resist lying on a wafer by the aforementioned electron beam lithography system or other system to form an LSI pattern, the electron beam deflection range of the system is up to only about 5 mm square for a single die, or chip, 10 to 20 mm square. Where a pattern of a structure such as an LSI gate chain is formed, it is necessary to form a pattern stitched (or connected) over the whole chip.
Accordingly, in order to form such a pattern, the stage carrying the wafer and the electrical deflection system are so controlled that pattern elements are stitched at intervals of 5 mm. Therefore, in the system shown in FIG. 1, the positioning deflector 10 is shown to consist of a single deflection system. In practice, a main (or primary) deflector for deflection at intervals of 5 mm is mounted. For deflection within a range less than 5 mm, a secondary deflection system or a ternary deflection system is provided. For example, the deflection range of the secondary deflection system is 500 μm. The deflection range of the ternary deflection system is 50 μm.
As a lithography system other than the variable-shaped beam lithography system shown in FIG. 1, a system using a cell projection lithography technique has been developed. In this system, an aperture having tens of patterns built therein is placed in the electron beam path. The electron beam passed through this aperture is reduced to {fraction (1/25)} and directed to a resist applied to the wafer. A pattern is written to a cell 5 μm square at maximum per shot. Since the shot position can be specified with arbitrary coordinates, a space may be formed between successive cells. The boundaries (or stitches or joints) between the successive cells can be brought into contact with each other. These boundaries are hereinafter referred to as shot boundaries. With this structure, any desired pattern ranging from a small pattern of 0.1 μm to a large pattern covering the whole chip can be drawn at will.
In the chip lithographically written by the aforementioned electron beam lithography system and having a size of 10 mm square, the number of field boundaries reaches 40,000. The number of boundaries of the cells amounts to 4 million. This is illustrated in FIG. 2, where a number of chips T are formed within a wafer W. Each chip T is virtually divided into main fields F1. Each main field F1 is virtually divided into subfields F2. Each subfield F2 is virtually divided into sub-subfields F3.
For example, the size of the chip T is 10 mm×10 mm. The size of each main field F1 is 5,000 μm ×5,000 μm. The size of each subfield F2 is 500 μm×500 μm. The size of each sub-subfield F3 is 50 μm×50 μm.
In the electron beam lithography system, the drawn region is virtually divided into smaller regions. The pattern is drawn for each smaller region. That is, after a certain region is written, the stage is moved, and then the main deflection system or secondary or ternary deflection system is so controlled as to write a pattern element to the adjacent region. As a result, the drawn pattern elements may be misaligned at the interface B (field boundary or shot boundary) between the adjacent different regions. The space between the pattern elements may produce an error.
FIGS. 3(a)-3(c) illustrate deviations of pattern elements at the field interface B. A pattern should be formed as shown in FIG. 3(a). The pattern elements may be misaligned in the Y-direction as shown in FIG. 3(b). As shown in FIG. 3(c), the pattern elements may be misaligned in the X-direction, thus splitting the pattern. In FIGS. 3(a)-3(c), the broken lines indicate the interface.
At the field interface in the pattern as shown in FIG. 3(b), the amount of allowable deviation is less than tenth the design dimension because of the performance of the LSI. For example, in the case of the pattern width of 0.1 μm, the allowable deviation is less than 10 nm. In FIG. 3(c), the pattern elements that should be stitched break. This is not allowed because of the actual performance of LSI. Where the amount of deviation is in excess of the maximum allowable value, the electron beam lithography system has a misadjustment. Therefore, it is necessary to find the misadjustment and to readjust the system.
In order to find where a fault is present within the electron beam lithography system, it is necessary that a pattern be drawn on the chips over the whole wafer, the numerous boundaries within the chips be inspected, and the amounts and directions of deviations of the pattern elements at the boundaries be measured. The results of the measurements permit misadjustments in the electron beam lithography system to be estimated empirically. If the misadjustments are found, then it is possible to readjust or repair the electron beam lithography system appropriately.